1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for an LCD device and a method of fabricating the same.
2. Discussion of the Related Art
Flat panel display (FPD) devices having high portability and low power consumption have been the subject of recent research and development. Liquid crystal display (LCD) devices are a type of FPD devices and are commonly used as monitors for notebook and desktop computers because of their ability to display high-resolution images, wide ranges of different colors, and moving images.
In most cases, an LCD device includes a color filter substrate and an array substrate separated from each other and having a liquid crystal layer interposed therebetween. The color filter substrate includes a common electrode and the array substrate includes a pixel electrode. When a voltage is supplied to the common electrode and the pixel electrode, an electric field is generated and changes the orientation of liquid crystal molecules of the liquid crystal layer due to optical anisotropy within the liquid crystal layer. Consequently, light transmittance characteristics of the liquid crystal layer are modulated and images are displayed by the LCD device.
Active matrix type LCD devices are commonly used because of their superiority in displaying moving images. Active matrix-type LCD devices include pixel regions disposed in a matrix. A thin film transistor (TFT) is formed in each pixel region and is a switching element. While forming the TFT, hydrogenated amorphous silicon (a-Si:H) is deposited over a large area of a substrate. Hydrogenated amorphous silicon yields higher productivity and is easily fabricated on the large area of the substrate. In addition, because the hydrogenated amorphous silicon (a-Si:H) is deposited at a relatively low temperature, an inexpensive glass substrate may be used. Accordingly, the hydrogenated amorphous silicon is commonly used in the TFT, and the TFT is referred to as an amorphous silicon thin film transistor (a-Si TFT).
However, because the atomic arrangement of the hydrogenated amorphous silicon is disordered, weak silicon-silicon (Si—Si) bonds and dangling bonds exist in the hydrogenated amorphous silicon. These types of bonds become metastable when light or an electric field is applied to the hydrogenated amorphous silicon. As a result, this metastability makes the TFT unstable. Electrical characteristics of hydrogenated amorphous silicon are especially degraded due to light irradiation. Furthermore, it is difficult to implement a TFT using hydrogenated amorphous silicon in a driving circuit because electric characteristics are degraded. These degraded electric characteristics include a relatively low field effect mobility and poor reliability.
To solve these problems, a polycrystalline silicon thin film transistor (p-Si TFT) may be employed. Due to a higher field effect mobility of a p-Si TFT compared to an a-Si TFT, a driving circuit and a switching element may be fabricated simultaneously. Accordingly, production costs are reduced and a driving circuit is simply fabricated on a substrate where a switching element is formed.
FIG. 1 is a schematic view showing an LCD device according to the related art where a switching element and a driving circuit are formed on a single substrate. In FIG. 1, a display area “D1” and a non-display area “D2” in a periphery of the display area “D1” are defined on a single substrate 10. The display area “D1” is disposed at a central portion of the substrate 10, while the non-display area “D2” is disposed at left and top portions of the display area “D1.” The non-display area “D2” includes a gate driving circuit 16 and a data driving circuit 18. The display area “D1” includes a plurality of gate lines 12 connected to the gate driving circuit 16 and a plurality of data lines 14 connected to the data driving circuit 18. The gate line 12 and the data line 14 cross each other to define a pixel region “P.” A pixel electrode 17 is formed in the pixel region “P.” A thin film transistor (TFT) “Ts” formed as a switching element is connected to the pixel electrode 17. The gate driving circuit 16 supplies a scan signal to the TFT “Ts” through the gate line 12 and the data driving circuit 18 supplies a data signal to the pixel electrode 17 through the data line 14.
The gate driving circuit 16 and the data driving circuit 18 are connected to an input terminal (not shown) to receive external signals. Accordingly, the gate driving circuit 16 and the data driving circuit 18 process the externals signals from the input terminal to generate the scan signal and the data signal. To generate the scan signal and the data signal, the gate driving circuit 16 and the data driving circuit 18 include a plurality of TFTs forming complementary metal-oxide-semiconductor (CMOS) elements. For example, an inverter including negative (n)-type and positive (p)-type TFTs may be formed in the gate driving circuit 16 and the data driving circuit 18.
FIG. 2 is a schematic plan view showing a display area of an array substrate for an LCD device according to the related art.
In FIG. 2, a gate line “GL” and a data line “DL” cross each other to define a pixel region “P” on a substrate 30. A thin film transistor “Ts” is connected to the gate line “GL” and the data line “DL.” A storage line “SL” is also shown. A pixel electrode 82 is connected to the thin film transistor “Ts.” For example, the thin film transistor “Ts” includes a gate electrode 52, a semiconductor layer 38, a source electrode 74a and a drain electrode 74b. The semiconductor layer 38 may include polysilicon material.
Further, a storage capacitor “Cst” including first, second and third storage electrodes 40, 54 and 76 and an intervening insulating layer (not shown) is formed in a portion of the pixel region “P.”
FIGS. 3A and 3B are schematic cross-sectional views showing an array substrate for an LCD device according to the related art where a switching element and a driving circuit are formed on a single substrate. FIG. 3B is a cross-sectional view taken along line “III-III” of FIG. 2.
In FIGS. 3A and 3B, in a non-display area “D2(DC),” a CMOS element consists of a positive (p)-type TFT “T(p)” and a negative (n)-type TFT “T(n).”
In a display area “D1,” a switching TFT “Ts” and a storage capacitor “Cst” are formed in one pixel region “P.” For example, the switching TFT “Ts” includes polysilicon material and is selected from an n-type TFT or a p-type TFT. The n-type TFT is usually utilized as the switching TFT “Ts.” The storage capacitor “Cst” may include first to third storage electrodes 40, 54 and 76 and intervening insulating layers 46 and 60 therebetween. The storage capacitor “Cst” includes first and second storage capacitors “C1” and “C2” connected to each other in parallel. Accordingly, the LCD device can obtain enough capacitance without increasing the structural size of the storage electrodes “Cst.”
For example, the array substrate may be manufactured through at least nine mask processes that includes doping the storage capacitor, doping with high concentration n-type impurities (n+), and doping with high concentration p-type impurities (p+).
The manufacturing process of the array substrate according to the related art will be explained referring to figures as follows: FIGS. 4A to 4I are schematic cross-sectional view showing a process of fabricating an array substrate in a non-display area for an LCD device according to the related art; FIGS. 5A to 5I are schematic plan views showing a process of fabricating an array substrate in a display area for an LCD device according to the related art; and FIGS. 6A to 6I are schematic cross-sectional views taken along a line “VI-VI” of FIG. 5A to 5I, respectively.
In FIGS. 4A, 5A and 6A, a substrate 30 includes a display area “D1” and a non-display area “D2.” The non-display area “D2” may be classified into a first region “A1” and a second region “A2,” and the display area “D1” may be classified into a third region “A3” and a fourth region “A4.” Here, the third region “A3” and the fourth region “A4” may constitute a pixel region “P.”
A buffer layer 32 is formed on the substrate 30.
Next, first, second, third and fourth semiconductor layers 34, 36, 38 and 40 are formed by depositing and crystallizing amorphous silicon material on the buffer layer 32 in the first to fourth regions “A1, A2, A3 and A4,” respectively, through a first mask process. Crystallizing the amorphous silicon material may be performed using a laser as a heat transfer means.
In FIG. 6A the third semiconductor layer 38 and the fourth semiconductor layer 40 are formed as one body.
Although not shown, the mask process includes coating a photoresist (PR) material layer, exposing and developing the PR material layer to form a PR pattern.
In FIGS. 4B, 5B and 6B, a first PR pattern 42 is formed on the first to fourth semiconductor layers 34, 36, 38 and 40 through a second mask process. Here, the first PR pattern 42 has an open portion exposing the fourth semiconductor layer 40. Next, the fourth semiconductor layer 40 exposed by the first PR pattern 42 in the fourth region “A4” is doped with high concentration n-type (n+) impurities while the first to third semiconductor layers 34, 36 and 38 are shielded by the first PR pattern 42.
Although not shown, the first PR pattern 42 is removed from the substrate 30 after doping.
In FIGS. 4C, 5C and 6C, a gate insulating layer 46 is formed over an entire surface of the substrate 30. Next, first, second and third gate electrodes 48, 50 and 52 and a first storage electrode 54 are formed on the gate insulating layer 46 through a third mask process. Specifically, the first to third gate electrodes 48, 50 and 52 may be disposed at central portions of the first to third semiconductor layers 34, 36 and 38, respectively.
For example, the gate insulating layer 46 includes an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material.
In this step, although not shown, a gate line connected to the third gate electrode 52 is formed and a storage line “SL” extended from the first storage electrode 54 is formed along a second direction parallel to the gate line. Substantially, the storage line “SL” is disposed to pass through the pixel region “P.”
In FIGS. 4D, 5D and 6D, a second PR pattern 56, which covers the first gate electrode 48 to correspond to the first semiconductor layer 34, is formed over the substrate 30 through a fourth mask process. That is, the second gate electrode 50, the third gate electrode 52 and the first storage electrode 54 are exposed by the second PR pattern 56.
Accordingly, the second semiconductor layer 36 and the third semiconductor layer 38 are selectively doped by the n(+) impurities while the first semiconductor layer 34 is shielded by the second PR pattern 56.
Although not shown, the second PR pattern 56 is removed from the substrate 30 after the doping.
In FIGS. 4E, 5E and 6E, a third PR pattern 58, which covers the second gate electrode 50 to correspond to the second semiconductor layer 36 and covers the third gate electrode 52 and the first storage electrode 54 to correspond to the third semiconductor layer 38 and the fourth semiconductor layer 40, is formed over the substrate 30 through a fifth mask process.
Accordingly, the exposed portion of the first semiconductor layer 34 is selectively doped with high concentration p-type (p+) impurities.
The doped portions of the first to fourth semiconductor layers 34, 36, 38 and 40 have an ohmic contact property.
Although not shown, the third PR pattern 58 is removed from the substrate 30 after the doping.
In FIGS. 4F, 5F and 6F, an interlayer insulating layer 60 is formed by depositing an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiOx), over an entire surface of the substrate 30.
In this step, the gate insulating layer 46 and the interlayer insulating layer 60 are etched to form first, second and third contact holes 62, 64 and 66 that expose both end portions of the first to third semiconductor layers 34, 36 and 38, respectively, through a sixth mask process. Specifically, the first to the third contact holes 62, 64 and 66 includes first source and first drain contact holes 62a and 62b, second source and second drain contact holes 64a and 64b and third source and third drain contact holes 66a and 66b, respectively.
In FIGS. 4G, 5G and 6G, first source and first drain electrodes 70a and 70b, second source and second drain electrodes 72a and 72b, third source and third drain electrodes 74a and 74b, and a second storage electrode 76 are formed by depositing and patterning a conductive metallic material layer such as chromium (Cr), molybdenum (Mo), tungsten (W), copper (Cu) or aluminum alloy (AlNd) on the interlayer insulating layer 60 through a seventh mask process. Specifically, the first source and the first drain electrodes 70a and 70b are connected to both of the doped end portions of the first semiconductor layer 34 via the first source and the first drain contact holes 62a and 62b, respectively.
Similarly, the second source and the second drain electrodes 72a and 72b are connected to the both of the doped end portions of the second semiconductor layer 36 via the second source and the second drain contact holes 64a and 64b, respectively. The third second source and the third drain electrodes 74a and 74b are connected to both of the doped end portions of the third semiconductor layer 38 via the third source and the third drain contact holes 66a and 66b, respectively.
Further, the second storage electrode 76 is extended from the third drain electrode 74b and is overlapped with the first storage electrode 54.
The first semiconductor layer 34, the first gate electrode 48, the first source electrode and the first drain electrode 70a and 70b may constitute a p-type thin film transistor “T(p)” in the first region “A1.” The second gate electrode 50, the second source electrode and the second drain electrode 72a and 72b may constitute an n-type thin film transistor “T(n)” in the second region “A2.” The p-type thin film transistor “T(p)” and the n-type thin film transistor “T(n)” constitute a CMOS element in the non-display area “D2.”
In addition, the third gate electrode 52, the third source electrode 74a and the third drain electrode 74b constitute a switching thin film transistor “Ts” in the third region “A3.” For example, the switching thin film transistor “Ts” may be an n-type thin film transistor.
Further, the fourth semiconductor layer 40 and the first storage electrode 54 with the gate insulating layer 46 form a first storage capacitor “C1.” The first storage electrode “C1” with the interlayer insulating layer 60 form a second storage capacitor “C2” in the fourth region “A4.” The first and the second storage capacitors “C1 and C2” constitute a storage capacitor “Cst.”
A data line “DL” connected to the third source electrode 74a is formed to cross the gate line “GL” to define the pixel region “P.”
In FIGS. 4H, 5H and 6H, a passivation layer 78 is formed over the substrate 30 and has a storage contact hole 80 that exposes a portion of the second storage electrode 76 through an eighth mask process.
In FIGS. 4I, 5I and 6I, a pixel electrode 82 is formed by depositing a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), on the passivation layer 78 and is disposed in the pixel region “P” through a ninth mask process. The pixel electrode 82 is connected to the second storage electrode 76 via the storage contact hole 80. Because the second storage electrode 76 is extended from the third drain electrode 74b, the pixel electrode 82 is connected to the third drain electrode 74b through the second storage electrode 76.
The second storage electrode 76 may substantially function as a storage electrode after being connected to the pixel electrode 82.
As explained above, the fabricating method of the array substrate according to the related art includes at least nine mask processes, thereby deteriorating the product yield by increasing product costs and product time. Further, because at least nine mask processes may be performed, the rate of defects may increase.